%0 Conference Paper %1 conf/asscc/LiDCWJSCC19 %A Li, An'an %A Ding, Yingtao %A Chen, Zipeng %A Wang, Wei %A Jiang, Sijia %A Sun, Shiyan %A Chen, Zhiming %A Chi, Baoyong %B A-SSCC %D 2019 %I IEEE %K dblp %P 153-156 %T A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2019.html#LiDCWJSCC19 %@ 978-1-7281-5106-9

@inproceedings{conf/asscc/LiDCWJSCC19, added-at = {2022-03-21T00:00:00.000+0100}, author = {Li, An'an and Ding, Yingtao and Chen, Zipeng and Wang, Wei and Jiang, Sijia and Sun, Shiyan and Chen, Zhiming and Chi, Baoyong}, biburl = {https://www.bibsonomy.org/bibtex/2564b36ee3a251ae968cf4a3f206d214b/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2019}, ee = {https://doi.org/10.1109/A-SSCC47793.2019.9056973}, interhash = {3262f70e3a9549b443b568af307c7466}, intrahash = {564b36ee3a251ae968cf4a3f206d214b}, isbn = {978-1-7281-5106-9}, keywords = {dblp}, pages = {153-156}, publisher = {IEEE}, timestamp = {2024-04-10T21:35:47.000+0200}, title = {A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2019.html#LiDCWJSCC19}, year = 2019 }