%0 Journal Article %1 journals/tvlsi/HaoNWY17 %A Hao, Cong %A Ni, Jianmo %A Wang, Nan %A Yoshimura, Takeshi %D 2017 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 1140-1153 %T Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#HaoNWY17 %V 25

@article{journals/tvlsi/HaoNWY17, added-at = {2020-03-11T00:00:00.000+0100}, author = {Hao, Cong and Ni, Jianmo and Wang, Nan and Yoshimura, Takeshi}, biburl = {https://www.bibsonomy.org/bibtex/22f7511c643c332f20448c9cff80815d8/dblp}, ee = {https://doi.org/10.1109/TVLSI.2016.2607758}, interhash = {37e7a4064700ef6322cc5940abfc8758}, intrahash = {2f7511c643c332f20448c9cff80815d8}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {1140-1153}, timestamp = {2020-03-12T11:43:36.000+0100}, title = {Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#HaoNWY17}, volume = 25, year = 2017 }