%0 Conference Paper %1 conf/islped/HeZJG11 %A He, Xun %A Zhou, Dajiang %A Jin, Xin %A Goto, Satoshi %B ISLPED %D 2011 %E Chang, Naehyuck %E Nakamura, Hiroshi %E Inoue, Koji %E Osada, Kenichi %E Poncino, Massimo %I IEEE/ACM %K dblp %P 373-378 %T A 98 GMACs/W 32-core vector processor in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/islped/islped2011.html#HeZJG11 %@ 978-1-61284-660-6

@inproceedings{conf/islped/HeZJG11, added-at = {2012-08-13T00:00:00.000+0200}, author = {He, Xun and Zhou, Dajiang and Jin, Xin and Goto, Satoshi}, biburl = {https://www.bibsonomy.org/bibtex/2808023fd3efd248014a0239b5f4d0cf3/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2011}, editor = {Chang, Naehyuck and Nakamura, Hiroshi and Inoue, Koji and Osada, Kenichi and Poncino, Massimo}, ee = {http://portal.acm.org/citation.cfm?id=2016891&CFID=34981777&CFTOKEN=25607807}, interhash = {886fd0e79e5d6b8b57731e1ebd810eb5}, intrahash = {808023fd3efd248014a0239b5f4d0cf3}, isbn = {978-1-61284-660-6}, keywords = {dblp}, pages = {373-378}, publisher = {IEEE/ACM}, timestamp = {2012-08-14T11:33:47.000+0200}, title = {A 98 GMACs/W 32-core vector processor in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2011.html#HeZJG11}, year = 2011 }