%0 Journal Article %1 journals/tcas/ZhouCXHLXLZY20 %A Zhou, Yongliang %A Cai, Hao %A Xie, Lei %A Han, Menglin %A Liu, Mingyue %A Xu, Shi %A Liu, Bo %A Zhao, Weisheng %A Yang, Jun %D 2020 %J IEEE Trans. Circuits Syst. I Fundam. Theory Appl. %K dblp %N 5 %P 1602-1614 %T A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI67.html#ZhouCXHLXLZY20 %V 67-I

@article{journals/tcas/ZhouCXHLXLZY20, added-at = {2020-05-22T00:00:00.000+0200}, author = {Zhou, Yongliang and Cai, Hao and Xie, Lei and Han, Menglin and Liu, Mingyue and Xu, Shi and Liu, Bo and Zhao, Weisheng and Yang, Jun}, biburl = {https://www.bibsonomy.org/bibtex/256f90d43ae436024e600494f0d4c7353/dblp}, ee = {https://doi.org/10.1109/TCSI.2019.2960028}, interhash = {da41e84d2ae14ac86dc0eceb171bb731}, intrahash = {56f90d43ae436024e600494f0d4c7353}, journal = {IEEE Trans. Circuits Syst. I Fundam. Theory Appl.}, keywords = {dblp}, number = 5, pages = {1602-1614}, timestamp = {2020-05-23T12:30:38.000+0200}, title = {A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI67.html#ZhouCXHLXLZY20}, volume = {67-I}, year = 2020 }