Design of Conditional Data Mapping Flip-Flop for Low Power Applications
K. Jindal, Renu, and V. Pandey. International Journal of Innovative Science and Modern Engineering (IJISME), 1 (5):
72-75(April 2013)
Abstract
Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24% reduction of clock driving power is achieved.
%0 Journal Article
%1 noauthororeditor
%A Jindal, Kanika
%A Renu,
%A Pandey, V. K.
%D 2013
%E Kumar, Dr. Shiv
%J International Journal of Innovative Science and Modern Engineering (IJISME)
%K CMOS Circuit. Flip Flop Low Power
%N 5
%P 72-75
%T Design of Conditional Data Mapping Flip-Flop for Low Power Applications
%U https://www.ijisme.org/wp-content/uploads/papers/v1i5/E0241041513.pdf
%V 1
%X Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24% reduction of clock driving power is achieved.
@article{noauthororeditor,
abstract = {Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24% reduction of clock driving power is achieved.},
added-at = {2021-09-22T13:31:37.000+0200},
author = {Jindal, Kanika and Renu and Pandey, V. K.},
biburl = {https://www.bibsonomy.org/bibtex/201f5653d14938f48a481b03f797d770a/ijisme_beiesp},
editor = {Kumar, Dr. Shiv},
interhash = {ca8718f75354394b4429191e23e86cf7},
intrahash = {01f5653d14938f48a481b03f797d770a},
issn = {2319-6386},
journal = {International Journal of Innovative Science and Modern Engineering (IJISME)},
keywords = {CMOS Circuit. Flip Flop Low Power},
language = {En},
month = {April},
number = 5,
pages = {72-75},
timestamp = {2021-09-22T13:31:37.000+0200},
title = {Design of Conditional Data Mapping Flip-Flop for Low Power Applications},
url = {https://www.ijisme.org/wp-content/uploads/papers/v1i5/E0241041513.pdf},
volume = 1,
year = 2013
}