%0 Journal Article %1 journals/tcad/MukhopadhyayBR06 %A Mukhopadhyay, Saibal %A Bhunia, Swarup %A Roy, Kaushik %D 2006 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 8 %P 1486-1495 %T Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#MukhopadhyayBR06 %V 25

@article{journals/tcad/MukhopadhyayBR06, added-at = {2024-05-07T00:00:00.000+0200}, author = {Mukhopadhyay, Saibal and Bhunia, Swarup and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/20c7ea4dc7908381e71fad316e943d5a6/dblp}, ee = {https://doi.org/10.1109/TCAD.2005.855934}, interhash = {64535646e38b95439304d8e5b9f426fc}, intrahash = {0c7ea4dc7908381e71fad316e943d5a6}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 8, pages = {1486-1495}, timestamp = {2024-05-13T07:26:45.000+0200}, title = {Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#MukhopadhyayBR06}, volume = 25, year = 2006 }