FPGA IMPLEMENTATION OF HIGH SPEED
BAUGH-WOOLEY MULTIPLIER USING
DECOMPOSITION LOGIC
A. Kiran, и N. Prashar. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal, 2 (3):
7(августа 2015)
Аннотация
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital
signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and
implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
%0 Journal Article
%1 kiran2015implementation
%A Kiran, Ananda
%A Prashar, Navdeep
%D 2015
%J Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
%K Baugh-Wooley Booth Decomposition Logic Multiplier
%N 3
%P 7
%T FPGA IMPLEMENTATION OF HIGH SPEED
BAUGH-WOOLEY MULTIPLIER USING
DECOMPOSITION LOGIC
%U http://airccse.com/eeiej/papers/2315eeiej01.pdf
%V 2
%X The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital
signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and
implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
@article{kiran2015implementation,
abstract = {The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital
signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and
implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
},
added-at = {2017-08-28T09:21:52.000+0200},
author = {Kiran, Ananda and Prashar, Navdeep},
biburl = {https://www.bibsonomy.org/bibtex/23d86c9784d644be74168e8ed394a1a50/kaety},
interhash = {10cbae9c2b68f42db576fbbe277dc233},
intrahash = {3d86c9784d644be74168e8ed394a1a50},
journal = {Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal},
keywords = {Baugh-Wooley Booth Decomposition Logic Multiplier},
month = {August},
number = 3,
pages = 7,
timestamp = {2017-08-28T09:21:52.000+0200},
title = {FPGA IMPLEMENTATION OF HIGH SPEED
BAUGH-WOOLEY MULTIPLIER USING
DECOMPOSITION LOGIC
},
url = {http://airccse.com/eeiej/papers/2315eeiej01.pdf},
volume = 2,
year = 2015
}