Conference,

NMS and Thresholding Architecture used for FPGA based Canny Edge Detector for Area Optimization

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(2013)

Abstract

In this paper, an architecture designed for Non- Maximal Suppression used in Canny edge detection algorithm is presented in order to reduce memory requirements significantly. The architecture also achieves decreased latency and increased throughput with no loss in edge detection. The new algorithm used has a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. Furthermore, the hardware architecture of the proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex 5 FPGA. The design development is done in VHDL and simulated results are obtained using modelsim 6.3 with Xilinx 12.2.

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