%0 Conference Paper %1 DinRen18Structured %A Ding, Caiwen %A Ren, Ao %A Yuan, Geng %A Ma, Xiaolong %A Li, Jiayu %A Liu, Ning %A Yuan, Bo %A Wang, Yanzhi %B Proceedings of the 2018 on Great Lakes Symposium on VLSI %D 2018 %K ASIC FFT FPGA LSTM architecture deep_learning hardware %P 353--358 %T Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs %U https://arxiv.org/pdf/1804.11239.pdf

@inproceedings{DinRen18Structured, added-at = {2019-01-11T10:43:31.000+0100}, author = {Ding, Caiwen and Ren, Ao and Yuan, Geng and Ma, Xiaolong and Li, Jiayu and Liu, Ning and Yuan, Bo and Wang, Yanzhi}, biburl = {https://www.bibsonomy.org/bibtex/24b514a867988b4938c4dcb465963db9c/loroch}, booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI}, interhash = {879ad53ca6143085f50fc0471e4f9f54}, intrahash = {4b514a867988b4938c4dcb465963db9c}, keywords = {ASIC FFT FPGA LSTM architecture deep_learning hardware}, organization = {ACM}, pages = {353--358}, timestamp = {2019-01-11T10:43:31.000+0100}, title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs}, url = {https://arxiv.org/pdf/1804.11239.pdf}, year = 2018 }