%0 Conference Paper %1 conf/cicc/RaviBCS04 %A Ravi, Ashoke %A Bishop, Ralph E. %A Carley, L. Richard %A Soumyanath, Krishnamurthy %B CICC %D 2004 %I IEEE %K dblp %P 625-628 %T 8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS. %U http://dblp.uni-trier.de/db/conf/cicc/cicc2004.html#RaviBCS04 %@ 0-7803-8495-4

@inproceedings{conf/cicc/RaviBCS04, added-at = {2017-08-21T00:00:00.000+0200}, author = {Ravi, Ashoke and Bishop, Ralph E. and Carley, L. Richard and Soumyanath, Krishnamurthy}, biburl = {https://www.bibsonomy.org/bibtex/2610ef03bcd7315ab26a4f4597510a1e6/dblp}, booktitle = {CICC}, crossref = {conf/cicc/2004}, ee = {https://doi.org/10.1109/CICC.2004.1358903}, interhash = {f16c650ceebb5fd0e5ebb0ad2092fdef}, intrahash = {610ef03bcd7315ab26a4f4597510a1e6}, isbn = {0-7803-8495-4}, keywords = {dblp}, pages = {625-628}, publisher = {IEEE}, timestamp = {2019-10-17T23:06:23.000+0200}, title = {8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2004.html#RaviBCS04}, year = 2004 }