%0 Journal Article %1 journals/corr/abs-1711-01263 %A Zhu, Jingyang %A Jiang, Jingbo %A Chen, Xizi %A Tsui, Chi-Ying %D 2017 %J CoRR %K FPGA acceleration architecture deep_learning sparse %T SparseNN: An Energy-Efficient Neural Network Accelerator Exploiting Input and Output Sparsity. %U https://link.springer.com/article/10.1007/s10766-017-0528-8 %V abs/1711.01263

@article{journals/corr/abs-1711-01263, added-at = {2018-06-16T11:40:00.000+0200}, author = {Zhu, Jingyang and Jiang, Jingbo and Chen, Xizi and Tsui, Chi-Ying}, biburl = {https://www.bibsonomy.org/bibtex/268b5966eb6f1192a7b21d201f57e49bc/loroch}, ee = {http://arxiv.org/abs/1711.01263}, interhash = {424df14cc6743f8b63c668dcba1f37c6}, intrahash = {68b5966eb6f1192a7b21d201f57e49bc}, journal = {CoRR}, keywords = {FPGA acceleration architecture deep_learning sparse}, timestamp = {2018-06-16T11:40:00.000+0200}, title = {SparseNN: An Energy-Efficient Neural Network Accelerator Exploiting Input and Output Sparsity.}, url = {https://link.springer.com/article/10.1007/s10766-017-0528-8}, volume = {abs/1711.01263}, year = 2017 }