%0 Journal Article %1 journals/tcad/KunzPR96 %A Kunz, Wolfgang %A Pradhan, Dhiraj K. %A Reddy, Sudhakar M. %D 1996 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 1 %P 20-32 %T A novel framework for logic verification in a synthesis environment. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#KunzPR96 %V 15

@article{journals/tcad/KunzPR96, added-at = {2020-09-24T00:00:00.000+0200}, author = {Kunz, Wolfgang and Pradhan, Dhiraj K. and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/2a0c2df3aa80bf09bbf7444044e134dd9/dblp}, ee = {https://doi.org/10.1109/43.486269}, interhash = {2c160a5272703ac0133bc56674c1bef9}, intrahash = {a0c2df3aa80bf09bbf7444044e134dd9}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 1, pages = {20-32}, timestamp = {2020-09-25T11:45:47.000+0200}, title = {A novel framework for logic verification in a synthesis environment.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#KunzPR96}, volume = 15, year = 1996 }