Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter
M. Radwene LAAJIMI. International Journal of Advanced Computer Science and Applications(IJACSA), (2012)
Abstract
This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35&\#181;m CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at &\#177;1.5V supply voltage.
%0 Journal Article
%1 IJACSA.2012.031118
%A Radwene LAAJIMI, Mohamed MASMOUDI
%D 2012
%J International Journal of Advanced Computer Science and Applications(IJACSA)
%K Analog-to-Digital CMOS Low Sigma-Delta amplifier. circuits; conversion; electronics; modulation; operational power switched-capacitor technology; transconductance
%N 11
%T Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter
%U http://ijacsa.thesai.org/
%V 3
%X This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35&\#181;m CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at &\#177;1.5V supply voltage.
@article{IJACSA.2012.031118,
abstract = {This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35\&\#181;m CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at \&\#177;1.5V supply voltage.},
added-at = {2014-02-21T08:00:08.000+0100},
author = {{Radwene LAAJIMI}, Mohamed MASMOUDI},
biburl = {https://www.bibsonomy.org/bibtex/2b90473d6a1307dfc474a23cde9f02dc8/thesaiorg},
interhash = {3928d123e62785f73fb685231f8d0343},
intrahash = {b90473d6a1307dfc474a23cde9f02dc8},
journal = {International Journal of Advanced Computer Science and Applications(IJACSA)},
keywords = {Analog-to-Digital CMOS Low Sigma-Delta amplifier. circuits; conversion; electronics; modulation; operational power switched-capacitor technology; transconductance},
number = 11,
timestamp = {2014-02-21T08:00:08.000+0100},
title = {{Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter}},
url = {http://ijacsa.thesai.org/},
volume = 3,
year = 2012
}