The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh
Network-on-Chip (NoC) of low-power RISC cores with minimal uncore
functionality. Whereas such a processor offers high computational energy
efficiency and parallel scalability, developing effective programming models
that address the unique architecture features has presented many challenges. We
present here a distributed shared memory (DSM) model supported in software
transparently using C++ templated metaprogramming techniques. The approach
offers an extremely simple parallel programming model well suited for the
architecture. Initial results are presented that demonstrate the approach and
provide insight into the efficiency of the programming model and also the
ability of the NoC to support a DSM without explicit control over data movement
and localization.
%0 Generic
%1 Richie2017Distributed
%A Richie, David
%A Ross, James
%A Infantolino, Jamie
%D 2017
%K hpc
%T A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor
%U http://arxiv.org/abs/1704.08343
%X The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh
Network-on-Chip (NoC) of low-power RISC cores with minimal uncore
functionality. Whereas such a processor offers high computational energy
efficiency and parallel scalability, developing effective programming models
that address the unique architecture features has presented many challenges. We
present here a distributed shared memory (DSM) model supported in software
transparently using C++ templated metaprogramming techniques. The approach
offers an extremely simple parallel programming model well suited for the
architecture. Initial results are presented that demonstrate the approach and
provide insight into the efficiency of the programming model and also the
ability of the NoC to support a DSM without explicit control over data movement
and localization.
@misc{Richie2017Distributed,
abstract = {{The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh
Network-on-Chip (NoC) of low-power RISC cores with minimal uncore
functionality. Whereas such a processor offers high computational energy
efficiency and parallel scalability, developing effective programming models
that address the unique architecture features has presented many challenges. We
present here a distributed shared memory (DSM) model supported in software
transparently using C++ templated metaprogramming techniques. The approach
offers an extremely simple parallel programming model well suited for the
architecture. Initial results are presented that demonstrate the approach and
provide insight into the efficiency of the programming model and also the
ability of the NoC to support a DSM without explicit control over data movement
and localization.}},
added-at = {2019-02-23T22:09:48.000+0100},
archiveprefix = {arXiv},
author = {Richie, David and Ross, James and Infantolino, Jamie},
biburl = {https://www.bibsonomy.org/bibtex/2bb6bcba98a6c5215c0d6cf8b932c1857/cmcneile},
citeulike-article-id = {14403528},
citeulike-linkout-0 = {http://arxiv.org/abs/1704.08343},
citeulike-linkout-1 = {http://arxiv.org/pdf/1704.08343},
day = 26,
eprint = {1704.08343},
interhash = {c65a0c58446950aaca100a079487b57c},
intrahash = {bb6bcba98a6c5215c0d6cf8b932c1857},
keywords = {hpc},
month = apr,
posted-at = {2017-07-31 10:13:05},
priority = {2},
timestamp = {2019-02-23T22:15:27.000+0100},
title = {{A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor}},
url = {http://arxiv.org/abs/1704.08343},
year = 2017
}