%0 Journal Article %1 noauthororeditor %A Tavazoei1, Mahdi %A and Farhad Razaghian1, %D 2019 %J International Journal of Electronic Design and Test (JEDT) %K Bit Boosted Half-select; Multi SRAM; Sub-threshold Vth interleaving; transistor voltage; %N 03 %P 01 to 11 %T A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH A SMALL AREA CONSUPTION %U https://airccse.com/jedt/papers/1319jedt01.pdf %V 01 %X In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal.

@article{noauthororeditor, abstract = {In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal. }, added-at = {2019-06-07T07:40:28.000+0200}, author = {Tavazoei1, Mahdi and and Farhad Razaghian1}, biburl = {https://www.bibsonomy.org/bibtex/2c74273eecff277aaa59860c883164e5c/jedtjournal}, interhash = {434861a16f8a3915062dc909e2ef9d40}, intrahash = {c74273eecff277aaa59860c883164e5c}, journal = {International Journal of Electronic Design and Test (JEDT) }, keywords = {Bit Boosted Half-select; Multi SRAM; Sub-threshold Vth interleaving; transistor voltage;}, language = {English}, month = may, number = 03, pages = {01 to 11}, timestamp = {2019-06-07T07:40:28.000+0200}, title = {A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH A SMALL AREA CONSUPTION}, url = {https://airccse.com/jedt/papers/1319jedt01.pdf}, volume = { 01 }, year = 2019 }