Article,
FPGA Architecture for Kriging Image Interpolation
International Journal of Advanced Computer Science and Applications(IJACSA), (2013)
Abstract
This paper proposes an ultrafast scalable embedded
image compression scheme based on discrete cosine transform.
It is designed for general network architecture that guarantees
maximum end-to-end delay (EED), in particular the Distributed
Multimedia Plays (DMP) architecture. DMP is designed to enable
people to perform delay-sensitive real-time collaboration from
remote places via their own collaboration space (CS). It requires
much lower EED to achieve good synchronization than that in
existing teleconference systems. A DMP node can drop packets
from networked CSs intelligently to guarantee its local delay and
degrade visual quality gracefully. The transmitter classifies visual
information in an input image into priority ranks. Included in the
bitstream as side information, the ranks enable intelligent packet
dropping. The receiver reconstructs the image from the remaining
packets. Four priority ranks for dropping are provided. Our
promising results reveal that, with the proposed compression
technique, maximum EED can be guaranteed with graceful
degradation of image quality. The given parallel designs for its
hardware implementation in FPGA shows its technical feasibility
as a module in the DMP architecture.
