Automatic Synthesis and Formal Verification of
Interfaces Between Incompatible Soft Intellectual
Properties
F. Boutekkouk. ACEEE Int. J. on Information Technology, (March 2013)
Abstract
In this work, we are concerned with automatic
synthesis and formal verification of interfaces between
incompatible soft intellectual properties (IPs) for System On
Chip (SOC) design. IPs Structural and dynamic aspects are
modeled via UML2.x diagrams such as structural, timing and
Statecharts diagrams. From these diagrams, interfaces are
generated automatically between incompatible IPs following
an interface synthesis algorithm. Interfaces behaviors
verification is performed by the model checker that is
integrated in Maude language. A Maude specification
including interface specification and properties for verification
are generated automatically from UML diagrams.
%0 Journal Article
%1 boutekkouk2013automatic
%A Boutekkouk, Fateh
%D 2013
%E ACEEE,
%J ACEEE Int. J. on Information Technology
%K Formal IP Integration Maude SOC UML verification
%N 1
%T Automatic Synthesis and Formal Verification of
Interfaces Between Incompatible Soft Intellectual
Properties
%U /brokenurl#doi.searchdl.org/01/IJIT/3/1/1145.pdf
%V 3
%X In this work, we are concerned with automatic
synthesis and formal verification of interfaces between
incompatible soft intellectual properties (IPs) for System On
Chip (SOC) design. IPs Structural and dynamic aspects are
modeled via UML2.x diagrams such as structural, timing and
Statecharts diagrams. From these diagrams, interfaces are
generated automatically between incompatible IPs following
an interface synthesis algorithm. Interfaces behaviors
verification is performed by the model checker that is
integrated in Maude language. A Maude specification
including interface specification and properties for verification
are generated automatically from UML diagrams.
@article{boutekkouk2013automatic,
abstract = {In this work, we are concerned with automatic
synthesis and formal verification of interfaces between
incompatible soft intellectual properties (IPs) for System On
Chip (SOC) design. IPs Structural and dynamic aspects are
modeled via UML2.x diagrams such as structural, timing and
Statecharts diagrams. From these diagrams, interfaces are
generated automatically between incompatible IPs following
an interface synthesis algorithm. Interfaces behaviors
verification is performed by the model checker that is
integrated in Maude language. A Maude specification
including interface specification and properties for verification
are generated automatically from UML diagrams.
},
added-at = {2013-03-09T08:08:53.000+0100},
author = {Boutekkouk, Fateh},
biburl = {https://www.bibsonomy.org/bibtex/2d6b9dbf46349862808ec996b6a6fa6f4/ideseditor},
editor = {ACEEE},
interhash = {9e76ab5972422b2a081516d167e93112},
intrahash = {d6b9dbf46349862808ec996b6a6fa6f4},
journal = {ACEEE Int. J. on Information Technology},
keywords = {Formal IP Integration Maude SOC UML verification},
month = mar,
number = 1,
timestamp = {2013-03-09T08:08:53.000+0100},
title = {Automatic Synthesis and Formal Verification of
Interfaces Between Incompatible Soft Intellectual
Properties
},
url = {/brokenurl#doi.searchdl.org/01/IJIT/3/1/1145.pdf},
volume = 3,
year = 2013
}