%0 Conference Paper %1 conf/vlsid/VermaD24 %A Verma, Anshul %A Das, Bishnu Prasad %B VLSID %D 2024 %I IEEE %K dblp %P 156-161 %T A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2024.html#VermaD24 %@ 979-8-3503-8440-6

@inproceedings{conf/vlsid/VermaD24, added-at = {2024-05-07T00:00:00.000+0200}, author = {Verma, Anshul and Das, Bishnu Prasad}, biburl = {https://www.bibsonomy.org/bibtex/2f7035e60981eae06f265217938c6601e/dblp}, booktitle = {VLSID}, crossref = {conf/vlsid/2024}, ee = {https://doi.org/10.1109/VLSID60093.2024.00032}, interhash = {532fe6684aba20c836b4a6db763d7d8a}, intrahash = {f7035e60981eae06f265217938c6601e}, isbn = {979-8-3503-8440-6}, keywords = {dblp}, pages = {156-161}, publisher = {IEEE}, timestamp = {2024-05-13T08:17:29.000+0200}, title = {A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2024.html#VermaD24}, year = 2024 }