%0 Journal Article %1 Gregg:2005:RegisterVM %A Gregg, David %A Beatty, Andrew %A Casey, Kevin %A Davis, Brian %A Nisbet, Andy %D 2005 %J Science of Computer Programming %K Bytecodes InstructionSet Interpreters Register %N 3 %P 319-338 %R 10.1016/j.scico.2004.08.005 %T The Case for Virtual Register Machines %U https://www.scss.tcd.ie/David.Gregg/papers/Gregg-SoCP-2005.pdf %V 57 %X Virtual machines (VMs) are a popular target for language implementers. A long-running question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter. Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduced the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads.

@article{Gregg:2005:RegisterVM, abstract = {Virtual machines (VMs) are a popular target for language implementers. A long-running question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter. Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduced the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads.}, added-at = {2021-08-29T18:54:09.000+0200}, author = {Gregg, David and Beatty, Andrew and Casey, Kevin and Davis, Brian and Nisbet, Andy}, biburl = {https://www.bibsonomy.org/bibtex/2625199134bf4c6c8bc0b20d00dbc2ef6/gron}, description = {The case for virtual register machines - ScienceDirect}, doi = {10.1016/j.scico.2004.08.005}, interhash = {5d85ba1f6186274d12bf0815b80444a6}, intrahash = {625199134bf4c6c8bc0b20d00dbc2ef6}, issn = {0167-6423}, journal = {Science of Computer Programming}, keywords = {Bytecodes InstructionSet Interpreters Register}, note = {Advances in Interpreters, Virtual Machines and Emulators}, number = 3, pages = {319-338}, timestamp = {2021-08-29T18:54:09.000+0200}, title = {The Case for Virtual Register Machines}, url = {https://www.scss.tcd.ie/David.Gregg/papers/Gregg-SoCP-2005.pdf}, volume = 57, year = 2005 }