Various Power Dissipation Techniques for CMOS Inverter
R. Rao. International Journal of Inventive Engineering and Sciences (IJIES)4
12-14 (June 2018)
Low power design of complex CMOS circuits is one of the major challenges that is being addressed and will be addressed in nanometer design era. With integration of millions and billions of transistors on a single chip, transistor density is drastically increasing that lead to more and more complexity in applications being implemented on a single chip. Design time is another major challenge that forces designers to address the need in a very short time optimizing chip performances. In order to ensure that the design is through in the first iteration, designers are banking on new methodologies and readymade solutions to optimize area, time and power. Hence, various power dissipation techniques for CMOS inverter circuit are investigated here.