%0 Journal Article %1 triptisharmashiwanisingh2011adder %A Tripti Sharma, Shiwani Singh, K. G. Sharma %A Singh, Prof. B. P. %D 2011 %E Das, Dr.Vinu V %J International journal on Recent trends in Engineering and technology %K adder %N 2 %P 3 %T New 9T Full Adder Design with 30% Reduced Threshold Loss %U /brokenurl#IJRTET.theaceeeorg %V 6 %X This paper is based on pre layout simulations of 8T and new proposed 9T full adder circuit that improves the performance of 8T adder by sacrificing the MOS transistor count by one. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power consumption hence power-delay product (PDP) and improves temperature sustainability when compared with an existing 8T adder. It also shows nearly 30% improvement in threshold loss as compared to 8T full adder. Therefore, in a nut shell proposed adder cell outperforms the existing 8T adder in super threshold region and proves to be a viable option for low power and energy efficient applications. All simulations are performed on 90nm standard model on Tanner EDA tool version 12.6.

@article{triptisharmashiwanisingh2011adder, abstract = {This paper is based on pre layout simulations of 8T and new proposed 9T full adder circuit that improves the performance of 8T adder by sacrificing the MOS transistor count by one. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power consumption hence power-delay product (PDP) and improves temperature sustainability when compared with an existing 8T adder. It also shows nearly 30% improvement in threshold loss as compared to 8T full adder. Therefore, in a nut shell proposed adder cell outperforms the existing 8T adder in super threshold region and proves to be a viable option for low power and energy efficient applications. All simulations are performed on 90nm standard model on Tanner EDA tool version 12.6. }, added-at = {2012-02-06T09:07:59.000+0100}, author = {{Tripti Sharma, Shiwani Singh}, K. G. Sharma and Singh, Prof. B. P.}, biburl = {https://www.bibsonomy.org/bibtex/207480efe97a0b705326720431abf1e24/idesajith}, editor = {Das, Dr.Vinu V}, interhash = {68c5f9d4919ee54ae040d9b8a6185e17}, intrahash = {07480efe97a0b705326720431abf1e24}, journal = {International journal on Recent trends in Engineering and technology}, keywords = {adder}, month = {NOVEMBER}, number = 2, pages = 3, timestamp = {2012-02-06T09:07:59.000+0100}, title = {New 9T Full Adder Design with 30% Reduced Threshold Loss }, url = {/brokenurl#IJRTET.theaceeeorg}, volume = 6, year = 2011 }