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%0 Journal Article
%1 journals/tvlsi/AliAC19
%A Ali, Muhammad
%A Ahmed, Mohammad A.
%A Chrzanowska-Jeske, Malgorzata
%D 2019
%J IEEE Trans. Very Large Scale Integr. Syst.
%K dblp
%N 3
%P 573-586
%T Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#AliAC19
%V 27
@article{journals/tvlsi/AliAC19,
added-at = {2020-03-11T00:00:00.000+0100},
author = {Ali, Muhammad and Ahmed, Mohammad A. and Chrzanowska-Jeske, Malgorzata},
biburl = {https://www.bibsonomy.org/bibtex/2fce1f70ebb09deb1d1b0a73a7292f8b1/dblp},
ee = {https://doi.org/10.1109/TVLSI.2018.2880322},
interhash = {77c58e218911ee5849c58df42750a436},
intrahash = {fce1f70ebb09deb1d1b0a73a7292f8b1},
journal = {IEEE Trans. Very Large Scale Integr. Syst.},
keywords = {dblp},
number = 3,
pages = {573-586},
timestamp = {2020-03-12T11:41:44.000+0100},
title = {Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#AliAC19},
volume = 27,
year = 2019
}