%0 Journal Article %1 journals/tvlsi/KorenK97 %A Koren, Zahava %A Koren, Israel %D 1997 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 3-14 %T On the effect of floorplanning on the yield of large area integrated circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi5.html#KorenK97 %V 5

@article{journals/tvlsi/KorenK97, added-at = {2020-03-11T00:00:00.000+0100}, author = {Koren, Zahava and Koren, Israel}, biburl = {https://www.bibsonomy.org/bibtex/28e6e38e86f42cfe076b54c6f3d740c7d/dblp}, ee = {https://doi.org/10.1109/92.555982}, interhash = {7dcc5f4b785346078d93a5c10e686b3b}, intrahash = {8e6e38e86f42cfe076b54c6f3d740c7d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {3-14}, timestamp = {2020-03-12T11:45:00.000+0100}, title = {On the effect of floorplanning on the yield of large area integrated circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi5.html#KorenK97}, volume = 5, year = 1997 }