%0 Journal Article %1 journals/tvlsi/TurnerW04 %A Turner, Richard H. %A Woods, Roger F. %D 2004 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 10 %P 1113-1118 %T Highly efficient, limited range multipliers for LUT-based FPGA architectures. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#TurnerW04 %V 12

@article{journals/tvlsi/TurnerW04, added-at = {2020-03-11T00:00:00.000+0100}, author = {Turner, Richard H. and Woods, Roger F.}, biburl = {https://www.bibsonomy.org/bibtex/2659da135f61a3c4d0ff9ada3429fa14c/dblp}, ee = {https://doi.org/10.1109/TVLSI.2004.833399}, interhash = {8a51b6e2011bbfd469fdc2feace86368}, intrahash = {659da135f61a3c4d0ff9ada3429fa14c}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 10, pages = {1113-1118}, timestamp = {2020-03-12T11:44:55.000+0100}, title = {Highly efficient, limited range multipliers for LUT-based FPGA architectures.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#TurnerW04}, volume = 12, year = 2004 }