Conference,
An Index-first Addressing Scheme for Multi-level Caches
(2013)
Abstract
Performance is one of the leading factors in the
current processor designs. A processor’s efficiency highly
depends upon the organization of its cache. In the multi-level
caches, the existing scheme of addressing the cache memory
produces a significant fraction of address conflicts at the lower
level cache. This increases the global miss rate which
diminishes the cache and processor performance. This problem
becomes more severe in multi-processing environment
because of conflicts of inter-process interference. An approach
that performs the cache addressing efficiently in multi-level
caches is proposed in this paper. The experimental results
show that this scheme significantly decreases the global miss
rate of the caches and the cycles per instruction (CPI)
performance metric of the processor.
