%0 Journal Article %1 M__2015 %A Salim, Shahina M. %A Lakhotiya, S. A. %D 2015 %I Auricle Technologies, Pvt., Ltd. %J International Journal on Recent and Innovation Trends in Computing and Communication %K Cryptosystem FPGA Mathematics Modular Multiplication RSA VHDL Vedic exponentiation %N 1 %P 162--164 %R 10.17762/ijritcc2321-8169.150134 %T A Review on Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics %U http://dx.doi.org/10.17762/ijritcc2321-8169.150134 %V 3 %X RSA is one of the most safest standard algorithm based on public key, for providing security in network. The hierarchical overlay multiplier is used in RSA circuitry for multiplication operation. The most significant aspect is the development of division architecture based on Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. Typically, modular-multiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. The implementation of RSA encryption/decryption algorithm using the algorithm of Ancient Indian Vedic Mathematics that have been modified to improve performance. RSA circuitry implemented using vedic multiplication is efficient in terms of area, speed compared to its implementation using conventional multiplication

@article{M__2015, abstract = {RSA is one of the most safest standard algorithm based on public key, for providing security in network. The hierarchical overlay multiplier is used in RSA circuitry for multiplication operation. The most significant aspect is the development of division architecture based on Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. Typically, modular-multiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. The implementation of RSA encryption/decryption algorithm using the algorithm of Ancient Indian Vedic Mathematics that have been modified to improve performance. RSA circuitry implemented using vedic multiplication is efficient in terms of area, speed compared to its implementation using conventional multiplication}, added-at = {2015-08-03T08:27:37.000+0200}, author = {Salim, Shahina M. and Lakhotiya, S. A.}, biburl = {https://www.bibsonomy.org/bibtex/2d0fc21d6d1c2ff8ae02c0235ca4982b0/ijritcc}, doi = {10.17762/ijritcc2321-8169.150134}, interhash = {a58cb06137e2f55c9639941079a73c21}, intrahash = {d0fc21d6d1c2ff8ae02c0235ca4982b0}, journal = {International Journal on Recent and Innovation Trends in Computing and Communication}, keywords = {Cryptosystem FPGA Mathematics Modular Multiplication RSA VHDL Vedic exponentiation}, month = {january}, number = 1, pages = {162--164}, publisher = {Auricle Technologies, Pvt., Ltd.}, timestamp = {2015-08-03T08:27:37.000+0200}, title = {A Review on Implementation of {RSA} Cryptosystem Using Ancient Indian Vedic Mathematics}, url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150134}, volume = 3, year = 2015 }