%0 Thesis %1 phd/ethos/McKechnie10 %A McKechnie, Paul Edward %D 2010 %K dblp %T Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems.

@phdthesis{phd/ethos/McKechnie10, added-at = {2022-04-05T00:00:00.000+0200}, author = {McKechnie, Paul Edward}, biburl = {https://www.bibsonomy.org/bibtex/2baf546087c3803bc453aaf42cb709d99/dblp}, ee = {https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.513302}, interhash = {ceb84bbd6fe209c934f257432b31ffa4}, intrahash = {baf546087c3803bc453aaf42cb709d99}, keywords = {dblp}, note = {British Library, EThOS}, school = {University of Glasgow, UK}, timestamp = {2024-04-09T08:58:32.000+0200}, title = {Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems.}, year = 2010 }