%0 Journal Article %1 ppenchalareddydrvthrimurthulu2014implementation %A P Penchala Reddy, Dr.V.Thrimurthulu, K. Jagadeesh Kumar %D 2014 %E ijer, %J International Journal of Engineering Research %K %N 12 %P 780-785 %T Implementation of Multi Mode AES Algorithm Using Verilog %U http://www.ijer.in/ijer/publication/v3s12/IJER_2014_1217.pdf %V 3 %X Increasing need of high security in communication led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. NIST in the beginning selected Rijndael within October 2000 and formal adoption as being the AES standard started in December 2001. FIPS PUB 197 explains a 128-bit block cipher making Ause of a 128, 192, or 256-bit key. In cryptography, modes of operation enable the repeated and secure use of a block cipher under a single key. This paper presents implementation of multi mode AES algorithm with three modes ECB, CBC and CTR modes. All these three modes are implemented with 128-bit plain text and 128 bit, 192 bit and 256 bit key lengths. Each program results are verified with ModelSim PE and are synthesized in Xilinx ISE 9.2i. These results are also useful for implementing hardware

@article{ppenchalareddydrvthrimurthulu2014implementation, abstract = {Increasing need of high security in communication led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. NIST in the beginning selected Rijndael within October 2000 and formal adoption as being the AES standard started in December 2001. FIPS PUB 197 explains a 128-bit block cipher making Ause of a 128, 192, or 256-bit key. In cryptography, modes of operation enable the repeated and secure use of a block cipher under a single key. This paper presents implementation of multi mode AES algorithm with three modes ECB, CBC and CTR modes. All these three modes are implemented with 128-bit plain text and 128 bit, 192 bit and 256 bit key lengths. Each program results are verified with ModelSim PE and are synthesized in Xilinx ISE 9.2i. These results are also useful for implementing hardware}, added-at = {2014-12-09T13:14:32.000+0100}, author = {{P Penchala Reddy, Dr.V.Thrimurthulu}, K. Jagadeesh Kumar}, biburl = {https://www.bibsonomy.org/bibtex/212e3aa28f9461d0c24e6d091c3fa29bd/tarunkumar681}, editor = {ijer}, interhash = {e7eb085f6eac7c9d95900c39fc44ea36}, intrahash = {12e3aa28f9461d0c24e6d091c3fa29bd}, journal = {International Journal of Engineering Research }, keywords = {}, month = {12}, number = 12, pages = {780-785 }, timestamp = {2014-12-09T13:14:32.000+0100}, title = {Implementation of Multi Mode AES Algorithm Using Verilog}, url = {http://www.ijer.in/ijer/publication/v3s12/IJER_2014_1217.pdf}, volume = 3, year = 2014 }