%0 Conference Paper %1 conf/cicc/ZhangWFSDXCL10 %A Zhang, Tao %A Wang, Kui %A Feng, Yi %A Song, Xiaodi %A Duan, Lian %A Xie, Yuan %A Cheng, Xu %A Lin, Youn-Long %B CICC %D 2010 %E Snyder, Jacqueline %E Patel, Rakesh %E Andre, Tom %I IEEE %K dblp %P 1-4 %T A customized design of DRAM controller for on-chip 3D DRAM stacking. %U http://dblp.uni-trier.de/db/conf/cicc/cicc2010.html#ZhangWFSDXCL10 %@ 978-1-4244-5758-8

@inproceedings{conf/cicc/ZhangWFSDXCL10, added-at = {2018-09-25T00:00:00.000+0200}, author = {Zhang, Tao and Wang, Kui and Feng, Yi and Song, Xiaodi and Duan, Lian and Xie, Yuan and Cheng, Xu and Lin, Youn-Long}, biburl = {https://www.bibsonomy.org/bibtex/2949a9ec766f9621bdc5f3f31ad5692a6/dblp}, booktitle = {CICC}, crossref = {conf/cicc/2010}, editor = {Snyder, Jacqueline and Patel, Rakesh and Andre, Tom}, ee = {https://doi.org/10.1109/CICC.2010.5617465}, interhash = {f33293b2aca59fcd9f52882e371d0b70}, intrahash = {949a9ec766f9621bdc5f3f31ad5692a6}, isbn = {978-1-4244-5758-8}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T23:09:30.000+0200}, title = {A customized design of DRAM controller for on-chip 3D DRAM stacking.}, url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2010.html#ZhangWFSDXCL10}, year = 2010 }