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A Fair Comparison of Adders in Stochastic Regime

, , , and . International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), IEEE, (2017)

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Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics, , , and . IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8 (4): 736-745 (2018)SRAM Test Chip for Radiation Experiment, , , , , and . Pan Pacific Symposium 2022, (2022)Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments, , , , , and . International Journal of Parallel Programming, 49 (4): 541--569 (Aug 1, 2021)A fair comparison of adders in stochastic regime., , , and . PATMOS, page 1-6. IEEE, (2017)Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction., , and . J. Syst. Archit., (2019)NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers, and . Embedded Computer Systems: Architectures, Modeling, and Simulation, page 103--119. Cham, Springer International Publishing, (2022)Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics, , , and . IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8 (4): 736-745 (2018)Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (4): 736-745 (2018)Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction., , and . J. Syst. Archit., (2019)FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework, , , , , and . International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), IEEE, (2017)