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Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.

, , , , and . MICRO, page 30-40. IEEE Computer Society, (2004)

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Cost-efficient soft error protection for embedded microprocessors., , , and . CASES, page 421-431. ACM, (2006)Scalable subgraph mapping for acyclic computation accelerators., , , and . CASES, page 147-157. ACM, (2006)Tolerating First Level Memory Access Latency in High-Performance Systems., , and . ICPP (1), page 36-43. CRC Press, (1992)The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs., , , , and . ICPP (2), page 142-145. CRC Press, (1991)StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs., , , and . IEEE Trans. Computers, 60 (1): 5-19 (2011)Sentinel Scheduling for VLIW and Superscalar Processors., , , , , , and . ACM Trans. Comput. Syst., 11 (4): 376-408 (1993)preliminary version: ASPLOS 1992: 238-247.Increasing hardware efficiency with multifunction loop accelerators., , , and . CODES+ISSS, page 276-281. ACM, (2006)Embracing heterogeneity with dynamic core boosting., and . Conf. Computing Frontiers, page 10:1-10:10. ACM, (2014)Low-cost prediction-based fault protection strategy., , , and . CGO, page 30-42. ACM, (2020)Multi-objective Exploration for Practical Optimization Decisions in Binary Translation., , , , and . ACM Trans. Embed. Comput. Syst., 18 (5s): 57:1-57:19 (2019)