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Disambiguation of "Ueno, Tomohiro"

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Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network.

, , , , , , , , , , , , , , , , , , , , , , , and . ASICON, page 1025-1028. IEEE, (2017)

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Keiko Ueno

Tomohiro Shibata

Chieko Ueno

Tomohiro Genka

Tomohiro Hayashi

 

Other publications of authors with the same name

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique., , , , , , and . IEEE J. Solid State Circuits, 50 (1): 68-80 (2015)Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing., , and . ACM Trans. Reconfigurable Technol. Syst., 10 (3): 18:1-18:22 (2017)A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI., , , , , , , , and . IEICE Trans. Electron., 99-C (6): 632-640 (2016)ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku., , , and . HPC Asia, page 140-150. ACM, (2023)Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area., , , , , , and . SC Workshops, page 1274-1278. ACM, (2023)FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks., , and . HEART, page 16:1-16:6. ACM, (2017)Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats., , and . DCC, page 345-354. IEEE, (2018)Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform., , , , and . CoRR, (2014)Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage., , , , , , and . FPT, page 1-4. IEEE, (2022)19.5 An HCI-healing 60GHz CMOS transceiver., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)