( en | de | ru )

 

Disambiguation of "Hoe, James C."

Author of the publication

copydeleteadd this publication to your clipboard
In-System FPGA Prototyping of an Itanium Microarchitecture.

, and . ICCD, page 288-294. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

James C Cornette

James C Russell

Rudolf Hoé

Michael James

Audrein James

 

Other publications of authors with the same name

Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration., and . CoRR, (2018)A Service-Oriented Memory Architecture for FPGA Computing., and . FPL, page 91-97. IEEE, (2020)SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture., , , , , , , , and . SIGMETRICS Perform. Evaluation Rev., 31 (4): 31-34 (2004)Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA., , , , , and . IEEE Trans. Computers, 72 (5): 1343-1355 (May 2023)A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem., , , , , , , , , and . CoRR, (2021)Operation-centric hardware description and synthesis.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2000)ndltd.org (oai:dspace.mit.edu:1721.1/86439).Dual use of superscalar datapath for transient-fault detection and recovery., , and . MICRO, page 214-224. ACM/IEEE Computer Society, (2001)Fast bilateral filtering by adapting block size., , , , and . ICIP, page 3281-3284. IEEE, (2010)Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration., and . FPL, page 230-234. IEEE Computer Society, (2018)Synthesis of Operation-Centric Hardware Descriptions., and . ICCAD, page 511-518. IEEE Computer Society, (2000)