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A Class of Graphs for Fault-Tolerant Processor Interconnections., and . ICDCS, page 448-460. IEEE Computer Society, (1984)A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set., and . IEEE Trans. Computers, 51 (11): 1282-1293 (2002)On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines., and . IEEE Trans. Computers, 49 (1): 88-94 (2000)On the Design of Pseudoexhaustive Testable PLA's., and . IEEE Trans. Computers, 37 (4): 468-472 (1988)Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units., , and . IEEE Trans. Computers, 53 (1): 83-88 (2004)On Totally Self-Checking Checkers for Separable Codes., and . IEEE Trans. Computers, 26 (8): 737-744 (1977)Test Generation for Multiple State-Table Faults in Finite-State Machines., and . IEEE Trans. Computers, 46 (7): 783-794 (1997)A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits., and . IEEE Trans. Computers, 48 (10): 1145-1152 (1999)Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission., and . IEEE Trans. Computers, 51 (7): 866-872 (2002)A Fault-Tolerant Communication Architecture for Distributed Systems., and . IEEE Trans. Computers, 31 (9): 863-870 (1982)