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The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (4): 846-852 (2007)A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell., , , and . IEEE J. Solid State Circuits, 54 (4): 1152-1160 (2019)12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , and 4 other author(s). ISSCC, page 210-211. IEEE, (2017)Comparison of child-human and child-computer interactions based on manual annotations., , , and . WOCCI, page 49-54. ISCA, (2009)Not-So-Latent Dirichlet Allocation: Collapsed Gibbs Sampling Using Human Judgments.. Mturk@HLT-NAACL, page 131-138. Association for Computational Linguistics, (2010)EE5: When will we stop driving our cars?, , , , and . ISSCC, page 524. IEEE, (2017)A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache., , , , and . ISSCC, page 315-324. IEEE, (2006)F2: 3D stacking technologies for image sensors and memories., , , , , and . ISSCC, page 512-513. IEEE, (2014)A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications., , , , , , , and . A-SSCC, page 185-188. IEEE, (2016)