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A tool set for the design of asynchronous circuits with bundled-data implementation.

, , , , and . ICCD, page 78-83. IEEE Computer Society, (2011)

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A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)., , , , , and . ACSD, page 50-55. IEEE, (2008)Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2790-2799 (2007)Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation., and . IEICE Trans. Electron., 95-C (4): 506-515 (2012)Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation., and . ACM Great Lakes Symposium on VLSI, page 157-162. ACM, (2011)A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation., , and . IEICE Trans. Electron., 96-C (4): 482-491 (2013)A tool set for the design of asynchronous circuits with bundled-data implementation., , , , and . ICCD, page 78-83. IEEE Computer Society, (2011)A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs., , , and . ISCAS, page 925-928. IEEE, (2010)A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation., , and . CIT, page 847-852. IEEE Computer Society, (2007)