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Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)High Performance Dense Ring Generators., , , and . IEEE Trans. Computers, 55 (1): 83-87 (2006)On Using Implied Values in EDT-based Test Compression., , , , and . DAC, page 11:1-11:6. ACM, (2014)EDT Bandwidth Management in SoC Designs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)Embedded deterministic test., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 776-792 (2004)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)Hardware Protection via Logic Locking Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)High Volume Diagnosis in Memory BIST Based on Compressed Failure Data., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 441-453 (2010)Embedded Deterministic Test for Low-Cost Manufacturing., , , , , and . IEEE Des. Test Comput., 20 (5): 58-66 (2003)Bicameral Mesh Gradation with a Controlled Advancing Front Approach., , and . Comput. Aided Des., (2022)