( en | de | ru )

 

Disambiguation of "Agrawal, Amogh"

Author of the publication

copydeleteadd this publication to your clipboard
RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing.

, and . SiPS, page 19-24. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Deepashri Agrawal

Mukesh Agrawal

Mudit Agrawal

Hemant Agrawal

Milan Agrawal

 

Other publications of authors with the same name

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2481-2494 (2020)Cuffless BP measurement using a correlation study of pulse transient time and heart rate., , and . ICACCI, page 1538-1541. IEEE, (2014)X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories., , and . CoRR, (2017)Proposal for a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets., , and . CoRR, (2018)X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks., , and . CoRR, (2019)Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives., , , , and . DATE, page 902-907. IEEE, (2021)IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (8): 2521-2531 (2020)Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays., , , and . IEEE Trans. Circuits Syst., 67-II (12): 3347-3351 (2020)Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 3064-3076 (2019)Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design., , , and . ISLPED, page 1-6. IEEE, (2021)