Author of the publication

s ADC, and DPLL in 32nm SoC CMOS.

Y. Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, H. Kim, B. Carlton, S. Suzuki, M. Shafi, Y. Palaskas, and H. Lakdawala. VLSIC, page 76-77. IEEE, (2012)

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Ravi Walli

Mylapore Ravi

Holger Raviol

Jewgeni Ravik

Samatha Ravipati

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A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.P. Madoglio, A. Ravi, H. Xu, K. Chandrashekar, M. Verhelst, S. Pellerano, L. Cuellar, M. Aguirre, M. Sajadieh, O. Degani and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS.Y. Li, C. Ornelas, H. Kim, H. Lakdawala, A. Ravi, and K. Soumyanath. ISSCC, page 70-72. IEEE, (2012)8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS.A. Ravi, R. Bishop, L. Carley, and K. Soumyanath. CICC, page 625-628. IEEE, (2004)A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.W. Li, H. Kim, K. Chandrashekar, K. Nguyen, and A. Ravi. ISLPED, page 1-6. IEEE, (2017)A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement.W. Tai, H. Xu, A. Ravi, H. Lakdawala, O. Degani, L. Carley, and Y. Palaskas. IEEE J. Solid State Circuits, 47 (7): 1646-1658 (2012)A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost.S. Kim, H. Krishnamurthy, S. Sofer, S. Weng, S. Wolf, A. Ravi, K. Ravichandran, O. Degani, J. Tschanz, and V. De. ISSCC, page 186-187. IEEE, (2023)A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.E. Thaller, R. Levinger, E. Shumaker, A. Farber, S. Bershansky, N. Geron, A. Ravi, R. Banin, J. Kadry, G. Horovitz and 5 other author(s). ISSCC, page 451-453. IEEE, (2021)A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.P. Madoglio, A. Ravi, L. Cuellar, S. Pellerano, P. Seddighrad, I. Lomeli, and Y. Palaskas. ESSCIRC, page 152-155. IEEE, (2009)A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control.W. Tai, H. Xu, A. Ravi, H. Lakdawala, O. Degani, L. Carley, and Y. Palaskas. ESSCIRC, page 131-134. IEEE, (2011)MIMO techniques for high data rate radio communications.Y. Palaskas, A. Ravi, and S. Pellerano. CICC, page 141-148. IEEE, (2008)

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Disambiguation of "Ravi, Ashoke"

Please choose a person to relate this publication to

Ravi Walli

Mylapore Ravi

Holger Raviol

Jewgeni Ravik

Samatha Ravipati

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ravi, Ashoke"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.

Please choose a person to relate this publication to

Ravi Walli

Mylapore Ravi

Holger Raviol

Jewgeni Ravik

Samatha Ravipati

Other publications of authors with the same name

Disambiguation