( en | de | ru )

 

Disambiguation of "Babighian, Pietro"

Author of the publication

copydeleteadd this publication to your clipboard
Interactive presentation: PowerQuest: trace driven data mining for power optimization.

, , and . DATE, page 1078-1083. EDA Consortium, San Jose, CA, USA, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Pietro Cortona

Pietro Moretto

Stefano Pietro

Pietro Cavallotti

Pietro Tierno

 

Other publications of authors with the same name

Interactive presentation: PowerQuest: trace driven data mining for power optimization., , and . DATE, page 1078-1083. EDA Consortium, San Jose, CA, USA, (2007)Low-overhead state-retaining elements for low-leakage MTCMOS design., , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2005)Systematic defect detection methodology for volume diagnosis: A data mining perspective., , , , and . ITC, page 1-10. IEEE, (2017)A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks., , and . DATE, page 500-505. IEEE Computer Society, (2004)Enabling fine-grain leakage management by voltage anchor insertion., , , and . DATE, page 868-873. European Design and Automation Association, Leuven, Belgium, (2006)Post-layout leakage power minimization based on distributed sleep transistor insertion., , , and . ISLPED, page 138-143. ACM, (2004)A scalable algorithm for RTL insertion of gated clocks based on ODCs computation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 29-42 (2005)Methodologies and techniques for power optimization of digital circuits.. Polytechnic University of Turin, Italy, (2006)Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating., , and . DATE, page 720-723. IEEE Computer Society, (2004)