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Disambiguation of "Reorda, Matteo Sonza"

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BASTION: Board and SoC test instrumentation for ageing and no failure found.

, , , , , , , , and . DATE, page 115-120. IEEE, (2017)

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Matteo Garavoglia

Matteo Rini

Matteo Gabba

Marco Matteo

Matteo Bertini

 

Other publications of authors with the same name

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)Software-Based Self-Test for Transition Faults: a Case Study., , , and . VLSI-SoC, page 76-81. IEEE, (2019)A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks., , , and . IEEE Trans. Computers, 69 (1): 87-98 (2020)Test-Plan Optimization for Flying-Probes In-Circuit Testers., , , and . ITC-Asia, page 19-24. IEEE, (2019)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability., , , and . J. Supercomput., 77 (10): 11625-11642 (2021)Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug., , , and . IET Comput. Digit. Tech., 4 (2): 104-113 (2010)A Functional Approach for Testing the Reorder Buffer Memory., , , and . J. Electron. Test., 30 (4): 469-481 (2014)Software-Based Testing for System Peripherals., , , , , and . J. Electron. Test., 28 (2): 189-200 (2012)A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits., , , , , and . J. Electron. Test., 33 (1): 25-36 (2017)