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Evolutionary Approach to Test Generation for Functional BIST, , , , and . CoRR, (2010)From RTL Liveness Assertions to Cost-Effective Hardware Checkers., , , and . DCIS, page 1-6. IEEE, (2018)Automated design error debug using high-level decision diagrams and mutation operators., , , , , and . Microprocess. Microsystems, 37 (4-5): 505-513 (2013)PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams., , , and . J. Electron. Test., 25 (6): 289-300 (2009)Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)Understanding multidimensional verification: Where functional meets non-functional., , , , , , and . Microprocess. Microsystems, (2019)Survey on Architectural Attacks: A Unified Classification and Attack Model., , , , and . CoRR, (2022)Hybrid Protection of Digital FIR Filters., , , , , , and . CoRR, (2023)RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems., , , , , , , , , and 8 other author(s). CoRR, (2019)A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks., , , , and . CoRR, (2023)