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Disambiguation of "Noel, Jean-Philippe"

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

, , , , , , , , , , , , , , , , , , , and . DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Jean-Noël Quintin

Jean-Noel Marsat

Jean-Noël Martin

Jean-Philippe Dubus

Jean-Philippe Kohl

 

Other publications of authors with the same name

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 50 (1): 125-136 (2015)High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (8): 2296-2306 (2017)Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2599-2607 (2018)A nonlinear state-space approach to hysteresis identification., , , and . CoRR, (2016)An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper., , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology., , , , , , and . VLSI-SoC, page 168-173. IEEE, (2013)Data-driven feedback linearisation using model predictive control., , , and . CoRR, (2022)Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges., , , , , , , and . ESSCIRC, page 83-86. IEEE, (2021)Binary ReRAM-based BNN first-layer implementation., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization., , , , , , , and . ISLPED, page 121-126. ACM, (2020)