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A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.

, , , , , , , and . ESSCIRC, page 343-346. IEEE, (2015)

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A 1.8-GHz instruction window buffer for an out-of-order microprocessor core., , , , , and . IEEE J. Solid State Circuits, 36 (11): 1628-1635 (2001)A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction., , , , , , , and . ESSCIRC, page 343-346. IEEE, (2015)A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology., , , , , , , , , and 4 other author(s). ESSCIRC, page 303-307. IEEE, (2017)A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2010)The vector fixed point unit of the synergistic processor element of the cell architecture processor., , , , , , and . ESSCIRC, page 203-206. IEEE, (2005)A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor., , , , , , , , , and 3 other author(s). ISSCC, page 344-345. IEEE, (2010)The vector fixed point unit of the synergistic processor element of the cell architecture processor., , , , , , and . DATE Designers' Forum, page 244-248. European Design and Automation Association, Leuven, Belgium, (2006)