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An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes., , , and . ISQED, page 249-256. IEEE, (2014)Design and application of multimodal power gating structures., and . ISQED, page 120-126. IEEE Computer Society, (2009)Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs., , and . ISQED, page 741-746. IEEE Computer Society, (2006)Maximizing Profit in Cloud Computing System via Resource Allocation., and . ICDCS Workshops, page 1-6. IEEE Computer Society, (2011)Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic., and . ISMVL, page 453-459. IEEE Computer Society, (2000)Post Layout Speed-up by Event Elimination., , and . ICCD, page 211-216. IEEE Computer Society, (1997)Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells., , and . ICCD, page 130-135. IEEE Computer Society, (1997)Achieving Energy Efficiency in Datacenters by Virtual Machine Sizing, Replication, and Placement., and . Advances in Computers, (2016)A Reinforcement Learning-Based Power Management Framework for Green Computing Data Centers., , and . IC2E, page 135-138. IEEE Computer Society, (2016)Interconnect Energy Dissipation in High-Speed ULSI Circuits., and . VLSI Design, page 132-. IEEE Computer Society, (2002)