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System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)Using branch handling hardware to support profile-driven optimization., , and . MICRO, page 12-21. ACM / IEEE Computer Society, (1994)Experimental Insights from the Rogues Gallery., , , , , and . ICRC, page 80-87. IEEE, (2019)A Power Model for Register-Sharing Structures., and . DIPES, volume 271 of IFIP, page 131-142. Springer, (2008)Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation., , and . IEEE Trans. Computers, 47 (6): 714-720 (1998)Iterative Modulo Scheduling., , , and . IEEE Micro, 38 (1): 115-117 (2018)Parallel Pattern Detection for Architectural Improvements., , and . HotPar, USENIX Association, (2011)Modeling Value Speculation: An Optimal Edge Selection Problem., , and . IEEE Trans. Computers, 52 (3): 277-292 (2003)Programming Strategies for Irregular Algorithms on the Emu Chick., , , , , , , , , and . CoRR, (2019)Compilers for Instruction-Level Parallelism., , , , , and . Computer, 30 (12): 63-69 (1997)