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Disambiguation of "Bellasi, David E."

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Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS.

, and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2322-2333 (2017)

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David E Hopkins

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Other publications of authors with the same name

An architecture for low-power compressed sensing and estimation in wireless sensor nodes., , , and . ISCAS, page 1732-1735. IEEE, (2014)Live demonstration: Real-time audio restoration using sparse signal recovery., , , , , and . ISCAS, page 659. IEEE, (2013)VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (3): 579-590 (2012)Sparsity-based real-time audio restoration., , , , , and . DASIP, page 1-2. IEEE, (2012)Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2322-2333 (2017)A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS., , , and . ISCAS, page 1-4. IEEE, (2017)A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1296-1305 (2015)Energy-Efficiency Analysis of Analog and Digital Compressive Sensing in Wireless Sensors., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (11): 2718-2729 (2015)A Broadband Multi-Mode Compressive Sensing Current Sensor SoC in 0.16 µm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 105-118 (2019)A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS., , , , , and . MWSCAS, page 101-104. IEEE, (2014)