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Fault-Tolerant Design of the IBM Power6 Microprocessor., , , , , , and . IEEE Micro, 28 (2): 30-38 (2008)A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)Voltage droop reduction using throttling controlled by timing margin feedback., , , , , and . VLSIC, page 96-97. IEEE, (2012)26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection., , , , , , , , , and . ISSCC, page 444-445. IEEE, (2017)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)IBM POWER9 processor and system features for computing in the cognitive era., , , , , , , , , and 3 other author(s). IBM J. Res. Dev., 62 (4/5): 1 (2018)Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology., , , and . IBM J. Res. Dev., 46 (1): 77-86 (2002)EnergyScale for IBM POWER6 microprocessor-based systems., , , , , , , , and . IBM J. Res. Dev., 51 (6): 775-786 (2007)Runtime power reduction capability of the IBM POWER7+ chip., , , , , , , , , and . IBM J. Res. Dev., (2013)Adaptive guardband scheduling to improve system-level efficiency of the POWER7+., , , , , and . MICRO, page 308-321. ACM, (2015)