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Disambiguation of "Satoh, Akashi"

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A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.

, , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2533-2541 (2013)

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Other publications of authors with the same name

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit., , and . GCCE, page 1-4. IEEE, (2016)High-speed hardware architectures for authenticated encryption mode GCM.. ISCAS, IEEE, (2006)High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching., , , , and . CHES, volume 4249 of Lecture Notes in Computer Science, page 187-200. Springer, (2006)Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI., and . ISC, volume 2433 of Lecture Notes in Computer Science, page 48-62. Springer, (2002)A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (1): 263-266 (2012)Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current., , , , , , , , , and . IEICE Trans. Electron., 95-C (6): 1089-1097 (2012)Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation., , and . IEEE SENSORS, page 1-4. IEEE, (2022)A Compact Rijndael Hardware Architecture with S-Box Optimization., , , and . ASIACRYPT, volume 2248 of Lecture Notes in Computer Science, page 239-254. Springer, (2001)High-Performance Concurrent Error Detection Scheme for AES Hardware., , , and . CHES, volume 5154 of Lecture Notes in Computer Science, page 100-112. Springer, (2008)Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function., , , and . ReConFig, page 223-228. IEEE Computer Society, (2011)