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Disambiguation of "Lu, Liqiang"

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Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs.

, , , , and . DAC, page 62:1-62:6. ACM, (2017)

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Lu Lu

Chison Lu

Baufa Lu

Longpei Lü

Jing Lu

 

Other publications of authors with the same name

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1177-1190 (April 2024)FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs., , , and . DAC, page 1-6. IEEE, (2020)Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs., , , , and . DAC, page 62:1-62:6. ACM, (2017)Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs., , , and . FCCM, page 101-108. IEEE Computer Society, (2017)Automatic Generation of Spatial Accelerator for Tensor Algebra., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (6): 1898-1911 (June 2023)Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture., , , , , , and . MICRO, page 977-991. ACM, (2021)SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAs., and . DAC, page 135:1-135:6. ACM, (2018)Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 857-870 (2020)Generating Systolic Array Accelerators With Reusable Blocks., , , and . IEEE Micro, 40 (4): 85-92 (2020)Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels., , , , and . IEEE Trans. Computers, 69 (7): 986-997 (2020)